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a admc200 functional block diagram reset wr a0? rd cs irq clk refout refin convst u v w aux pwmsync a ap b bp c cp stop embedded control sequencer internal reference 11-bit a/d converter 12-bit pwm timer block control registers vector transformation block databus control bus d0 ?d11 motion coprocessor information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. features analog input block 11-bit resolution analog-to-digital (a/d) converter 4 single-ended simultaneously sampled analog inputs 3.2 s conversion time/channel 0 v? v analog input range internal 2.5 v reference pwm synchronized sampling capability 12-bit pwm timer block three-phase center-based pwm 1.5 khz?5 khz pwm switching frequency range programmable deadtime programmable pulse deletion pwm synchronized output external pwm shutdown vector transformation block 12-bit vector transformations forward and reverse clarke transformations forward and reverse park rotations 2.9 s transformation time dsp & microcontroller interface 12-bit memory mapped registers twos complement data format 6.25 mhz to 25 mhz operating clock range 68-lead plcc package single 5 v dc power supply industrial temperature range general description the admc200 is a motion coprocessor that can be used with either microcontrollers or digital signal processors (dsp). it provides the functionality that is required to implement a digital control system. in a typical application, the dsp or micro- controller performs the control algorithms (position, speed, torque and flux loops) and the admc200 provides the neces- sary motor control functions: analog current data acquisition, vector transformation, and pwm drive signals. product highlights simultaneous sampling of four inputs a four channel sample and hold amplifier allows three-phase motor currents to be sampled simultaneously, reducing errors from phase coherency. sample and hold acquisition time is 1.6 s and conversion time per channel is 3.2 s (using a 12.5 mhz system clock). one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ?analog devices, inc., 2000 flexible analog channel sequencing the admc200 support acquisition of 2, 3, or 4 channels per group. converted channel results are stored in registers and the data can be read in any order. the sampling and conversion time for two channels is 8 s, three channels is 11.2 s, and four channels is 14.4 s (using a 12.5 mhz system clock). embedded control sequencer the embedded control sequencer off-loads the dsp or micro- processor, reducing the instructions required to read analog in- put channels, control pwm timers and perform vector trans- formations. this frees the host processor for performing control algorithms. fast dsp/microprocessor interface the high speed digital interface allows direct connection to 16-bit digital signal processors and microprocessors. the admc200 has 12 bit memory mapped registers with twos complement data format and can be mapped directly into the data memory map of a dsp. this allows for a single instruction read and write interface. integration the admc200 integrates a four channel simultaneous sam- pling analog-to-digital converter, analog reference, vector trans- formation, and three-phase pwm timers into a 68-lead plcc. integration reduces cost, board space, power consumption, and design and test time. rev. b obsolete
admc200?pecifications (v dd = +5 v 5%; agnd = dgnd = 0 v; refin = 2.5 v; external clock = 12.5 mhz; t a = ?0 c to +85 c unless otherwise noted) parameter admc200ap units conditions/comments analog-to-digital converter 1 resolution 11 bits twos complement data format relative accuracy 2 lsb max integral nonlinearity differential nonlinearity 2 lsb max bias offset error 5 lsb max any channel bias offset match 4 lsb max between channels full-scale error 6 lsb max any channel full-scale error match 4 lsb max between channels conversion time/channel 40 system clk cycles signal-to-noise ratio (snr) 2 60 db min f in = 600 hz sine wave, f sample = 55 khz, 600 hz channel-to-channel isolation sine wave applied to unselected channels two-/three-phase mode ?8 db max three-/three-phase mode ?5 db max analog inputs input voltage level 0? volts analog input current 100 a max input capacitance 10 pf typ track and hold aperture delay 200 ns max any channel aperture time delay match 20 ns max between channels sha acquisition time 20 system clk cycles droop rate 5 mv/ms max reference input voltage level 2.5 v dc reference input current 50 a max reference output voltage level 2.5 volts voltage level tolerance 5 % max full load drive capability 200 a max logic v il 0.8 v max v ih 2.0 v min v ol 0.4 v max i sink = 400 a, v dd = 5 v v oh 4.5 v min i source = 20 a, v dd = 5 v input leakage current 1 a max three-state leakage current 1 a max input capacitance 20 pf typ pwm timers resolution 12 bits programmable deadtime range 0?0.08 s programmable deadtime increments 2 system clk cycles 160 ns programmable pulse deletion range 0?0.16 s programmable deletion increments 1 system clk cycle 80 ns minimum pwm frequency 1.5 khz resolution varies with pwm switching frequency (10 mhz clock: 20 khz = 9 bits, 10 khz = 10 bits, 5 khz = 11 bits, 2.5 khz = 12 bits). higher fre- quencies are available with lower resolution vector transformation park & clarke transformation radius error 0.7 % max angular error 30 arc min max reverse transformation time 37 system clk cycles forward transformation time 40 system clk cycles external clock input range 6.25?5 mhz if > 12.5 mhz, then it is necessary to divide down via sysctrl register internal system clock range 6.25?2.5 mhz power supply current i dd 20 ma max notes 1 measurements made with external reference. 2 tested with pwm switching frequency of 25 khz. specifications subject to change without notice. rev. b ? obsolete
admc200 rev. b ? 9 table i. timing specifications (v dd = 5 v 5%; t a = 4 0 c to +85 c) number symbol timing requirements min max units 1t per clk clk period 40 160 ns 2t pwh clk clk pulsewidth, high 20 ns 3t pwl clk clk pulsewidth, low 20 ns 4t su csb_wrb cs low before falling edge of wr 0ns 5t su addr_wrb addr valid before falling edge of wr 0n s 6t su data_wrb data valid before rising edge of wr 13 ns 7t hd wrb_data data hold after rising edge of wr 4.5 ns 8t hd wrb_addr addr hold after rising edge of wr 4.5 ns 9t hd wrb_csb cs hold after rising edge of wr 4.5 ns 10 t pwl wrb 1 wr pulsewidth, low 20 ns 11 t pwh wrb 1 wr pulsewidth, high 20 ns 12 t hd wrb_clk_h 1 wr low after rising edge of clk 7 ns 13 t su wrb_clk_h 1 wr high before rising edge of clk 7 ns 14 t su wrb_clk_l 1 wr high before falling edge of clk 10 ns 15 t hd clk_wrb_l 1 wr high after falling edge of clk 10 ns 16 t su csb_rdb cs low before falling edge of rd 0ns 17 t su addr_rdb addr valid before falling edge of rd 0n s 18 t hd rdb_addr addr hold after rising edge of rd 0n s 19 t hd rdb_csb cs hold after rising edge of rd 0ns 20 t pwl rdb rd pulsewidth, low 20 ns 21 t pwh rdb rd pulsewidth, high 20 ns 22 t su rdb_clk_h rd low before rising edge of clk 7.5 ns 23 t hd rdb_clk_h rd low after rising edge of clk 7.5 ns 24 t pwl resetb reset pulsewidth, low 2 t per clk ns note 1 all writes to the admc200 must occur within 1 system clock cycle (0 wait states). number symbol switching characteristics min max units 25 t dly rdb_data data valid after falling edge of rd 23 ns 26 t hd rdb_data data hold after rising edge of rd 0n s 11 4 5 6 7 10 12 15 13 9 8 14 clk cs a0a3 wr data note: all writes to the admc200 must occur within one system clock cycle (i.e. 0 wait states) figure 3. write cycle timing diagram 1 2 3 clk figure 1. clock input timing 24 clk reset figure 2. reset input timing obsolete
admc200 rev. b 4 ordering guide part temperature package package number range description option admc200ap ?0 c to +85 c 68-lead plcc p-68a 23 25 26 16 clk cs a0a3 rd data 22 20 21 18 19 17 figure 4. read cycle timing diagram absolute maximum ratings* supply voltage (v dd ) . . . . . . . . . . . . . . . . . . ?.3 v to +7.0 v digital input voltage . . . . . . . . . . . . . . . . . . . . . ?.3 v to v dd analog input voltage . . . . . . . . . . . . . . . . . . . . . ?.3 v to v dd analog reference input voltage . . . . . . . . . . . . ?.3 v to v dd digital output voltage swing . . . . . . . . . . . . . . ?.3 v to v dd analog reference output swing . . . . . . . . . . . . ?.3 v to v dd operating temperature . . . . . . . . . . . . . . . . . ?0 c to +85 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . +280 c *stresses greater than those listed above may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the admc200 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device obsolete
admc200 rev. b 5 pin mnemonic type description 1 d9 bidir data bit 9 2 d10 bidir data bit 10 3 d11 bidir data bit 11, msb 4? nc no connect 10 v dd sup +5 v digital power supply 11 a3 i/p address bit 3, msb 12 a2 i/p address bit 2 13 a1 i/p address bit 1 14 a0 i/p address bit 0, lsb 15 nc no connect 16 reset i/p chip reset 17 convst i/p a/d conversion start 18 irq o/p interrupt request (pu ll-up required) 19 v dd sup +5 v digital power supply 20 dgnd gnd digital ground 21 clk i/p external clock input 22 wr i/p write select 23 rd i/p output enable/read 24 cs i/p chip select 25 nc no connect 26 v dd sup +5 v analog power supply 27 agnd gnd analog ground 28 agnd gnd analog ground 29 u i/p analog input u 30 v i/p analog input v 31 w i/p analog input w 32 sgnd gnd analog signal ground 33 refin i/p analog reference input 34?6 nc no connect 37 aux i/p auxiliary analog input 38 refout o/p internal 2.5 v analog reference 39 v dd sup +5 v digital power supply 40 dgnd gnd digital ground pin mnemonic type description 41 dgnd gnd digital ground 42 dgnd gnd digital ground 43 dgnd gnd digital ground 44 v dd sup +5 v digital power supply 45 nc no connect 46 dgnd gnd digital ground 47 stop i/p pwm timer output disable 48 pwmsync o/p pwm synchronization output 49 cp o/p pwm timer output c prime 50 c o/p pwm timer output c 51 bp o/p pwm timer output b prime 52 nc no connect 53 b o/p pwm timer output b 54 ap o/p pwm timer output a prime 55 a o/p pwm timer output a 56 dgnd gnd digital ground 57 dgnd gnd digital ground 58 dgnd gnd digital ground 59 v dd sup +5 v digital power supply 60 d0 bidir data bit 0, lsb 61 d1 bidir data bit 1 62 d2 bidir data bit 2 63 d3 bidir data bit 3 64 d4 bidir data bit 4 65 d5 bidir data bit 5 66 d6 bidir data bit 6 67 d7 bidir data bit 7 68 d8 bidir data bit 8 pin types pin types i/p = input pin bidir = bidirectional pin o/p = output pin sup = supply pin gnd = ground pin pin designations pin configuration 10 11 12 13 14 15 16 17 18 19 20 22 23 24 25 26 21 96 1 8765 68676665646362 4321 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 43 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 pin 1 identifier top view (not to scale) d0 v dd dgnd dgnd dgnd a ap b nc bp c cp pwmsync stop dgnd nc v dd sgnd agnd agnd u v w refin nc nc nc aux refout v dd dgnd dgnd dgnd dgnd v dd a3 a2 a1 a0 nc reset convst irq v dd dgnd clk wr rd cs nc v dd nc = no connect nc nc nc nc d11 d7 d4 d6 d5 d1 nc nc d8 d9 d2 d3 d10 admc200 obsolete
admc200 rev. b 6 registers respectively. the twos complement data is left justified and the lsb is set to zero. the relationship between input volt- age and output coding is shown in figure 5. 011111111110 000000000000 100000000000 output code full-scale transition 0v 2.5 5v1lsb input voltage fs = 5v lsb = 5v 2048 figure 5. transfer function sample and hold after powering up the admc200, bring the reset pin low for a minimum of two clock cycles in order to enable a/d conver- sions. before initiating the first conversion (convst) after a reset, the sha time of 20 system clock cycles must occur. a conversion is initiated by bringing convst high for a mini- mum of one system clock cycle. the sha goes into hold mode at the falling edge of clock. following completion of the a/d conversion process, a mini- mum of 20 system clock cycles are required before initiating an- other conversion in order to allow the sample and hold circuitry to reacquire the input signals. if a convst is initiated before the 20 clock cycles have elapsed, the embedded control sequencer will delay conversion until this requirement is met. pwm timer block overview the pwm timers have 12-bit resolution and support program- mable pulse deletion and deadtime. the admc200 generates three center-based signals a, b, and c based upon user-supplied duty cycles values. the three signals are then complemented and adjusted for programmable deadtime to produce the six outputs. the admc200 pwm master switching frequency can range from 2.5 khz to 20 khz, when using a 10 mhz system clock. the master frequency selection is set as a fraction of the pwmtm register. if the system clock is 10 mhz, then the minimum edge resolution available is 100 ns. the output format of the pwm block is active lo. there is an external input to the pwm timers (stop) that will disable all six outputs within one system clock when the input is high. the admc200 has a pwm synchronization output (pwmsync) w hich brings out the master switching frequency from the pwm timers. the width of the pwmsync pulse is equal to one system clock cycle. for example, if the system clock is 10 mhz, the pwmsync width would be equal to 100 ns. pwm master switching period selection the switching time is set by the pwmtm register which should be loaded with a value equal to the system clock frequency divided by the desired master switching frequency. for ex- ample, if the desired switching frequency is 8 khz and the sys- tem clock freque ncy is 10 mhz, then the pwmtm register should be loaded with 1250 (10 mhz/8 khz). the pwmcha, pwmchb, and pwmchc registers are loaded with the analog input block the admc200 contains an 11-bit resolution, successive approxi- mation analog-to-digital (a/d) converter with twos complement output data format. the analog input range is 2.5 v (0 v? v) with a 2.5 v offset as defined by refin. the on-chip 2.5 v 5% reference is utilized by connecting the refout pin to the refin pin. the a/d conversion time is determined by the system clock fre- quency, which can range from 6.25 mhz to 12.5 mhz. the sample and hold (sha) acquisition time is 20 system clock cycles and is independent of the number of channels sampled and/or digitized. the input stage to the a/d converter is a four channel sha which allows the four channels to be held simulta- neously and then sequentially digitized. forty system clock cycles are required to complete each a/d conversion. the ana- log channel sampling is flexible and is programmable through the sysctrl register. the minimum number of channels per conversion is two. the throughput time of the analog acquisi- tion block can be calculated as follows: t aa = t sha + ( n t conv ) where t aa = analog acquisition time, n = # channels, t sha = sha acquisition time (20 system clock period), t conv = conversion time (40 system clock period) per channel. a/d conversions are initiated via the convst pin. a syn- chronizing pulse (pwmsync) is provided at the beginning of each pwm cycle. this pulse can be used to synchronize the a/d conversion process to the pwm switching frequency. operating the a/d converter the a/d converter can be set up to convert a sequence of chan- nels as defined in the sysctrl register (see table v). always write 0 to both bits 0 and 1 of the sysctrl register. the de- fault channel select mode after reset is to convert channels v and w only. this is two-/three-phase mode. three-/three-phase mode converts channels u, v, w and/or aux. three-/three- phase mode is achieved by writing a 1 to bit 3 of the sysctrl register. after the conversion process is complete, the channels can be read in any order. there are two methods that can be used to indicate when the a/d conversions are completed and the data is ready: interrupt driven and software timing. interrupt driven method interrupts can be used to indicate the end of conversion for a group of channels. before beginning any a/d conversions, bit 7 of the sysctrl register must be set to 1 to enable a/d con- version interrupts. then, when an a/d conversion is complete, an interrupt will be generated. after an interrupt is detected bit 0 of the sysstat register must be checked to determine if the a/d converter was the source. reading the sysstat reg- ister automatically clears the interrupt flag bits. software timing method an alternative method is to use the dsp or microcontroller to keep track of the amount of time elapsed between convst and the expected completion time (n t conv ). reading results the 11-bit a/d conversion results for channels u, v, w and aux are stored in the adcu, adcv, adcw and adcaux obsolete
admc200 rev. b 7 desired on-time and their values would be calculated as a ratio of the pwmtm register value. note: desired pulse density = (pwmchx register)/( pwmtm register). the beginning of each pwm cycle is marked by the pwmsync signal. new values of pwmcha, pwmchb and pwmchc must all be loaded into their respective registers at least four sys- tem clock cycles before the beginning of a new pwm cycle. all three registers must be updated for any of them to take effect. new pwm on/off times are calculated during these four clock cycles and therefore the pwmcha, pwmchb and pwmchc registers must be loaded before this time. if this timing require- ment is not met, then the pwm outputs may be invalid during the next pwm cycle. pwm example the following example uses a system clock speed of 10 mhz. the desired pwm master switching frequency is 8 khz and the desired on-time for the timers a, b and c are 25%, 50% and 10% respectively. the values for the pwmcha, pwmchb, and pwmchc registers must be calculated as ratios of the pwmtm register (1250 in this example). to achieve these duty cycles, load the pwmcha register with 313 (1250 0.25), pwmchb with 625 (1250 0.5) and pwmchc with 125 (1250 0.1). programmable deadtime with perfectly complemented pwm drive signals and nonideal switching characteristics of the power devices, both transistors in a particular leg might be switched on at the same time, result- ing in either a power supply trip, inverter trip or device destruc- tion. in order to prevent this, a delay must be introduced between the complemented signal edges. for example, the ris- ing edge of ap occurs before the falling edge of a, and the fall- ing edge of the complemented a occurs after the rising edge of a. this capability is known as programmable deadtime. the admc200 programmable deadtime value is loaded into the 7-bit pwmdt register, in which the lsb is set to zero in- ternally, which means the deadtime value is always divisible by two. with a 10 mhz system clock, the 0 126 range of values in pwmdt yield a range of deadtime values from 0 s to 12.6 s in 200 ns steps. figure 6 shows pwm timer a with a program- mable deadtime of pwmdt. pwmcha - pwmdt a pwmtm ap pwmcha + pwmdt figure 6. programmable deadtime example pulse deletion the pulse deletion feature prevents a pulse from being gener- ated when the user-specified duty cycle results in a pulse dura- tion shorter than the user-specified deletion value. the pulse deletion value is loaded into the 7-bit register pwmpd. when the user-specified on-time for a channel would result in a calcu- lated pulsewidth less than the value specified in the pwmpd register, then the pwm outputs for that channel would be set to full off (0%) and its prime to full on (100%). this is valid for a, ap, b, bp, c and cp. this feature would be used in an en- vironment where the inverter s power transistors have a mini- mum switching time. if the user-specified duty cycle would result in a pulse duration shorter than the minimum switching time of the transistors, then pulse deletion should be used to prevent this occurrence. with a 10 mhz system clock, the 0 127 range of values in pwmpd yield a range of deadtime values from 0 s to 12.7 s in 100 ns steps. external pwm shutdown there is an external input pin (stop) to the pwm timers that will disable all six outputs when it goes high. when the stop pin goes high, the pwm timer outputs will all go high within one system clock cycle. when the stop pin goes low, the pwm timer outputs are re-enabled within one system clock cycle. if external pwm shutdown isn t required, tie the stop pin low. vector transformation block overview the vector transformation block performs both park and clarke coordinate transformations to control a three-phase motor (permanent magnet synchronous motor or induction motor) via independent control of the decoupled rotor torque and flux currents. the park and clarke transformations combine to convert three-phase stator current signals into two orthogonal rotor referenced current signals i d and i q . i d represents the flux or magnetic field current and iq represents the torque generat- ing current. the i d and i q current signals are used by the processor s motor torque control algorithm to calculate the required d irect v d and quadrature v q voltage components for the motor. the forward park and clarke transformations are used to convert the v d and v q voltage signals in the rotor reference frame to three phase voltage signals (u, v, w) in the stator reference frame. these are then scaled by the processor and written to the admc200 s pwm registers in order to drive the inverter. the figures below illustrate the clarke and park trans- formations respectively. i w i u i v i y i x 120 120 120 three-phase equivalent stator currents two-phase currents figure 7. reverse clarke transformation i y i x i q i d rotor reference frame axis 90 rotating stationary reference frame reference frame figure 8. reverse park transformation obsolete
admc200 rev. b 8 v q v d v y v x 90 stationary rotating reference frame reference frame figure 9. forward park transformation v y v x w u v 120 120 120 equivalent three-phase stator two-phase voltage voltage figure 10. forward clarke transformation operating/using the vector transformation block after powering up the admc200, reset must be driven low for a minimum of two clock cycles to enable vector transformations. the vector transformation block can perform either a forward or reverse transformation. reverse transformation is defined by the following operations: (a) clarke: 3-phase current signals to 2-phase current signals followed by (b) park: 2-phase current signals cross multiplied by sin , cos which effectively measures the current components with respect to the rotor (stationary) where is the electrical angle of the rotor field with respect to the stator windings. forward transformation is defined by the following operations: (a) park: 2-phase voltage signals cross multiplied by sin , cos followed by (b) clarke: 2-phase to 3-phase voltage signal conversion. in order to provide maximum flexibility in the target system, the admc200 operates in an asynchronous manner. this means that the functional blocks (analog input, reverse transformation, forward transformation and pwm timers) operate indepen- dently of each other. the reverse and forward vector transfor- mation operations cannot occur simultaneously. all vector transformation registers, except for rho/rhop, are twos complement. rho/rhop are unsigned ratios of 360 . for ex- ample, 45 would be 45/360 2 12 . performing a reverse transformation a reverse transformation is initiated by writing to the reverse rotation angle register rho and operates on the values in the phip1, phip2 and phip3 registers. when the reverse trans- formation is in 2/3 mode, phip1 is calculated from phip2 and phip3. this is used in systems where only two phase currents are measured. the reverse transformation 2/3 mode is set by clearing bit 10 in the sysctrl register and is the default mode after reset . in order to perform a reverse transformation, first write to the phip2 and phip3 registers, and to the phip1 register if not in 2/3 mode. then initiate the transformation by writing the re- verse rotation angle to the rho register. the reverse rotation will be completed in 37 system clock cycles after the rotation is initiated. if bit 6 of the system control reg- ister is set, then an interrupt will be generated on completion. when an interrupt occurs, the user must check bit 1 of the sysstat register to determine if the vector transformation block was the source of the interrupt. during the vector transformation, the vector transformation registers must not be written to or the vector rotation results will be invalid. reverse clarke transformation the first operation is the clarke transformation in which the three phase motor current signals (i u , i v , i w ) are converted to sine and cosine orthogonal signals (i x and i y ). these signals represent the equivalent currents in a two-phase ac machine and is the signal format required for the park rotation. the three- phase input signals are of the form: phip1 i u = i s cos phip2 i v = i s cos ( + 120) phip3 i w = i s cos ( + 240) and the park rotation requires inputs in the form i s cos and i s sin , therefore we need to generate i s sin . this is calculated from: iy i s sin = 1 3 ( i s cos ( + 240) i s cos ( +120)) after the reverse transform, registers i x and i y contain the 2- phase input current information. in the case where 2 of 3-phase information (phip2/3 only) is provided, then phip1 will be derived from the simple fact that all sum to zero. this value is then placed in the ix register. ix = i x = i s cos = i s cos ( + 120) i s cos ( + 240) reverse park rotation ix/iy are then processed together with the digital angle (rho) by a park rotation. if the input signals are i x and i y , then the rotation can be described by: id i d = i x cos + i y sin iq i q = i y sin + i y cos where id and iq are the outputs of the park rotation. cos and sin are required for the park rotation, and are cal- culated internally. substituting for i x and i y in the above yields: id i d = i s cos cos + i s sin sin = i s cos ( ) iq i q = i s sin cos i s cos sin = i s sin ( ) performing a forward transformation in order to perform a forward rotation, write values to the vd and vq registers and then initiate the transformation by writing the rotation angle to the register rhop. the forward transfor- mation will only operate correctly when bit 10 in the sysctrl register is set (i.e., in 3/3 mode). the forward rotation will be completed in 40 system clock cycles after the rotation is initiated. if bit 6 of the system con- trol register is set, then an interrupt w ill be generated on obsolete
admc200 rev. b 9 completion. when an interrupt occurs, the user must check bit 1 of the system status register, sysstat, to determine if the vector transformation block was the source of the interrupt. during the vector transformation, the transformation registers must not be written to or the vector rotation results will be i nvalid. forward park rotation if the input signals are represented by v d and v q , then the trans- formation can be described by: vx v x = v d cos v q sin vy v y = v d sin + v q cos where v x and v y are the outputs of the park rotation, and are the inputs to the reverse clarke transformation. forward clarke transformation (2 to 3 phase) the second operation to be applied to the above results, is the forward clarke transformation where 2 phase (stator) voltage signals are converted to 3 phase (stator) voltage signals. for the inverse clarke transform we require three phase out- puts of the form below: phv1 v cos phv2 v cos ( + 120) phv3 v cos ( + 240) we have two quadrature voltages (v cos and v sin ) available. phv2 v cos ( + 120) = 1 2 v cos 3 2 v sin phv3 v cos ( + 240) = 1 2 v cos + 3 2 v sin interrupt generation there are two interrupt sources on the admc200 that may be independently enabled to generate interrupts. the first interrupt source is the analog input block, which, if enabled, generates an interrupt at the end of conversion. the second in- terrupt source is the vector transformation block, which, if enabled, generates an interrupt at the end of a vector transformation. when a 1 is stored in bit 7 of the sysctrl register, adc interrupts are enabled. when a 1 is stored in bit 6 of the sysctrl register, vector transformation interrupts are en- abled. upon a reset of the chip, both bits are set to the default condition, 0, thus disabling all interrupts. when an enabled interrupt occurs, bit 11 of the sysstat register becomes a 1. if that interrupt had been an adc inter- rupt, bit 0 of sysstat register would also be set to 1. if that interrupt had been a vector transformation interrupt, bit 1 of sysstat would be set to 1. whenever the sysstat register is read, these three bits go back to their default state, 0, immedi- ately after their values are loaded onto the data bus. upon a re- set, these three bits also go to their default state, 0. the irq pin has an open-drain driver, which will drive it low at the appropriate times, but the user must supply an external pull-up resistor to bring the node back high when it is not being pulled low. the irq pin operates in one of two modes, edge mode or level mode. in edge mode, when an enabled interrupt occurs, the irq pin will be driven low for one system clock period. in level mode, when an enable interrupt occurs, the irq pin will be driven low, and will remain low until the sysstat register is read. the combination of level mode and the open-drain driver allows multiple interrupt sources in an application to drive a single interrupt input line on the host dsp or microprocessor. edge mode or level mode is determined with bit 8 of the sysctrl register. edge mode (0) is the default; a 1 in this bit will put the irq pin into level mode. the recommended method of using the interrupt generation capability is to set edge or level mode, enable the appropriate interrupts, and then monitor the irq line. after the irq pin goes low, the sysstat register of the admc200 should be read, (1) to determine if it was this chip that caused the inter- rupt, if other lines are wired together with this irq pin, and (2) if it was this chip, to determine if it was generated by the analog input block or the vector transformation block. once this is done, the appropriate interrupt handling routine may be executed. application note list 1. an-407 ac motor control experiments using the admc200 evaluation board 2. an-408 ac motor control using the admc200 motion coprocessor 3. an-409 advanced motor control techniques using the admc200 motion coprocessor power supply connections and setup the nominal positive power supply level (v dd ) is +5 v 5%. the positive power supply v dd should be connected to all admc200 v dd pins (10, 19, 26, 39, 44, 59). the sgnd pin (32) and both agnd pins (27, 28) should be star point con- nected at a point close to the agnd pins of the admc200. the dgnd pins (20, 40, 41, 42, 43, 46, 56, 57, 58) should also be connected to agnd pins close to the admc200. power supplies should be decoupled at the power pins using a 0.1 f capacitor. a 220 nf capacitor must also be connected as close as possible between refin (pin 33) and sgnd (pin 32). in addition, the irq requires a 15 k pull-up to the v dd supply. dsp/controller interface the admc200 has a 12 bit bidirectional parallel port for inter- facing with analog devices adsp-2100 dsp family or micro- controllers/microprocessors. the admc200 coprocessor is designed to be conveniently in- terfaced to adi s family of fixed-point dsps. figures 11 and 12 show the interfacing between the admc200 and the adsp- 2101/2105/2115, adsp-2171, adsp-2181, tms320c2x dsps. in the case of the tms320c2x, some glue logic is re- quired to decode the rd/ wr lines and invert the clkout1 signal. the adsp-2101/2105/2115 clkout frequency equals the crystal/clock frequency of its clkin. this signal (clkout) can be used to directly drive the clk line (pin 21) on the admc200. the admc200 coprocessor can be operated with a clock frequency between the range of 6.25 mhz and 25 mhz. if the clock frequencies are greater than 12.5 mhz, then it is necessary to internally divide down the external clock to derive the admc200 s system clock (via sysctrl register). obsolete
admc200 rev. b 10 in the case of the adsp-2171/2181, the system clock is inter nally scaled; a 10 mhz system clock will derive a 20 mhz clkout. in the case of the tms320c2x, the clkout1 signal is derived from the system clock divided by a factor of 4; c onsequently a 50 mhz tms320c25-50 will derive a 12.5 mhz clkout1 for use by the admc200. note: a pull-up resistor is required on the irq (pin 18) output from the admc200. the stop (pin 47) must be tied low if not in use. system clock frequency the nominal range of the input clock for the admc200 is 6.25 mhz to 25 mhz. the external clk frequency can be in- ternally divided down by 2 by writing to bit 5 of the sysctrl register. if the external clk is faster than 12.5 mhz then it is necessary to internally divide it down. register addressing four address lines (a0 through a3) are used in conjunction with the control lines ( cs , wr , rd ,) to select registers 0 through 15. the cs and rd control lines are active low. the registers are given symbolic names. table ii. pin function cs enables the admc200 register interface (connect via chip select logic-active low) rd places data from the internal register onto the data bus wr loads the internal register with data on the data bus on its positive edge en address decode v dd dms irq2 rd wr clkout d0d23 a0a13 adsp-2101/ adsp-2105/ adsp-211520mhz adsp-218110mhz adsp-217110mhz cs irq rd wr clk d0d11* a0a3 admc200 address bus data bus *note: by mapping the admc200 data bus to the twelve highest bits of the adsp data bus, full-scale outputs from the adc can be represented by 1.0 in fixed point arithmetic. figure 11. adi digital signal processor/microcomputer en address decode v dd is intn strb r/w clkout1 d0d15 a0a15 tms320c20 tms320c25-50 tms320c25 cs irq rd wr clk d0d11 a0a3 admc200 address bus data bus figure 12. ti second-generation devices tms320c20/ c25/c25 50 table iii. write registers name a 3 a 2 a 1 a 0 register function rho 0000 l oad rho ( ) and start reverse transform phip1/vd 0001 r everse rotation direct input/forward direct input phip2/vq 0010 r everse rotation direct input/forward direct input phip3 0011 r everse rotation direct input rhop 0100 l oad rhop( ) and start forward transform pwmtm 0101 pwm m aster switching period pwmcha 0110 pwm c hannel a on-time pwmchb 0111 pwm c hannel b on-time pwmchc 1000 pwm c hannel c on-time pwmdt 1001 pwm programmable deadtime (7-bit register) pwmpd 1010 pwm pu lse deletion value (7-bit register) 1011 r eserved 1100 r eserved sysctrl 1101 s ystem control 1110 r eserved 1111 r eserved obsolete
admc200 rev. b 11 description of the registers all unspecified register locations are reserved. sysctrl system control register (see table v and vi) sysstat system status register (see table vii) adcu these registers contain the results from the first adcv three analog input channels u, v, and w. the adcw output data format is twos complement and therefore bit 0 is always zero as the a/d converter has 11-bit resolution. adcaux this register contains the conversion result of the auxiliary channel. pwmtm pwm master switching period pwmcha pwm channel a on-time pwmchb pwm channel b on-time pwmchc pwm channel c on-time pwmdt pwm programmable deadtime value pwmpd pwm programmable pulse deletion v alue id/iq these are the results of the reverse rotation (torque and flux components). phv1/2/3 these are the results from the forward clarke transformation. phip1/2/3 the inputs for reverse vector transformation (clarke and park). ix/iy these registers contain the results of the clarke transformation that are the inputs to the reverse park rotation. vx, vy vx , vy contain the results of the forward park rotation. rhop rhop is the angle used during the forward vec- tor transformation. writing to the rhop regis- ter causes the forward rotation to start based on values in rhop, vd and vq registers. rho rho is the angle used during the reverse vector transformation. writing to this register starts the reverse rotation using the values in the rho, phip1/2/3 registers. rho and rhop are unsigned ratios of 360 . for example, 45 degrees w ould be 45/360 2 12 . table iv. read registers name a 3 a 2 a 1 a 0 register function id/phv1/vx 0000 r everse rotation result (i ds )/forward result cos +0 iq/phv2 0001 r everse rotation result (i qs )/forward cos +120 ix/phv3 0010 r everse clarke cos + 0 /forward result cos +240 iy/vy 0011 r everse clarke cos +90 /forward cos +90 0100 r eserved adcv 0101 a/d c onversion result channel v adcw 0110 a/d c onversion result channel w adcaux 0111 a/d c onversion result auxiliary channel adcu 1000 a/d c onversion result channel u 1001 r eserved 1010 r eserved 1011 r eserved 1100 r eserved sysctrl 1101 system control sysstat 1110 system status 1111 r eserved table v. system control (sysctrl) registers reset bit function default 0 reserved, must be 0 0 1 reserved, must be 0 0 3 enables u channel conversion (1 = enable) three/three-phase mode 0 4 enables aux channel conversion (0 = disable, 1 = enable) 0 5 divide external clock by 2 (0 = no, 1 = yes) 0 6 park interrupt enable 0 7 adc interrupt enable (0 = disable, 1 = enable) 0 8 irq pin format (edge or level based interrupt requests) (0 = edge) 0 10 reverse rotation (0 = 2/3, 1 = 3/3) forward rotation (1 = enable) 0 bit 0, 1 reserved for future use. always write 0 to these bits. bit 3 channel u conversion enable. if bit 3 is set to 1, then channel u will be converted along with v, w and/or aux. this bit selects three-/three-phase mode. bit 4 aux channel conversion enable. if bit 4 is set to 1, then the aux input will be converted along with the channels v, w and/or u. bit 5 if bit 5 = 1, then the external clock will be divided by two to derive the system clock. if the external clock frequency is greater than 12.5 mhz, then this bit must be set. bit 6 park interrupt enable. this bit allows interrupts to be generated when the park rotation is completed. bit 7 adc interrupt enable. this bit allows interrupts to be generated via the irq pin when the analog-to- digital conversion process is complete. obsolete
admc200 rev. b 12 table vii. system status register (sysstat) 1 reset bit function default 0 a/d conversion completion interrupt (1 = true) 0 1 vector transformation completion interrupt (1 = true) 0 4 rotation results are valid (1 = valid) x 2 11 irq generated from this 0 device (1 = true) notes 1 reading this register clears the interrupt status flags bits 0, 1 and 11. 2 undefined until the first vector transformation has started bit 0 a/d conversion completion interrupt. this register is set to 1 when the a/d conversion process has com- pleted and adc interrupts have been enabled in the sysctrl register. bit 1 interrupt status. this register is set to 1 when the vector transformation is completed and the vector transformation completion interrupts have been enabled. bit 4 this bit is set to 1 when the rotation results are valid. bit 11 if any interrupt source on the admc200 occurs, then this bit is set to 1. c2071a 1.5 4/00 (rev. b) printed in u.s.a. outline dimensions dimensions shown in inches and (mm). 68-lead plastic leaded chip carrier (plcc) (p-68a) 9 pin 1 identifier 10 61 60 26 27 44 43 top view (pins down) 0.995 (25.27) 0.985 (25.02) sq 0.954 (24.23) 0.950 (24.13) sq 0.019 (0.48) 0.017 (0.43) 0.050 (1.27) typ 0.925 (23.50) 0.895 (22.73) 0.029 (0.74) 0.027 (0.69) 0.104 (2.64) typ 0.175 (4.45) 0.169 (4.29) bottom view (pins up) pin 1 identifier table vi. sysctrl analog input channel selection bit 3 bit 4 channels converted mode 0 0 v, w (default) two/three phase 0 1 v, w, aux two/three phase 1 0 u, v, w three/three phase 1 1 u, v, w, aux three/three phase bit 8 irq pin format edge or level interrupt selection. if bit 8 is set to 0, then an interrupt will cause a pulse of one system clock to be generated on the irq pin. if bit 8 is set to 1, then an interrupt causes the irq output to go low (logic 0). the irq output pin will remain low until the sysstat register is read. bit 10 if bit 10 is set to 1, then the reverse park transforma- tion will be formed in 3/3 m ode. for forward transformations, this bit must be set to 1. obsolete

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